This invention relates to multiprocessor cache coherence management.
Referring to FIG. 1, a shared-memory multiprocessor system 10 includes processing modules 12 connected to an interconnection network 14. Each processing module 12 includes a processor 121 and a cache 122, which is a fast memory directly accessible to the associated processor 121 in the same processing module 12. Cache 122 holds copies of data that have been recently accessed, and are likely to be accessed soon by its associated processor 121. Before a processor 121 reads a data block, the processor first goes to its cache 122 to see if the data block has already been placed there. If the data block is not in its cache 122, called a cache miss, or the data block is not valid, the processor must retrieve the data block from either a local or remote memory unit 16 through the interconnection network 14. The interconnection network 14 is typically a bus or a general Local Area Network (LAN) that delivers data to its destination according to a destination address sent with the data. An I/O controller 18, also connected to the interconnection network 14, serves as an I/O interface to various types of I/O devices.
The multiprocessor system 10 includes memory units 16, each coupled to, or associated with, one of the processing modules 12. The memory units 16 are shared by all of the processors 121, that is, every processor 121 can read from or write to any of memory units 16. However, only the processor 121 associated with, i.e., locally connected to, a memory unit 16 has local access to that memory unit; all the other processors 121 have to access it remotely through the interconnection network 14.